In recent years, the printed circuit boards for the high density mounting of miniaturized electronic components has been actively developed under the trend of reducing size and weight of electronic equipment having high performance.
Especially the economical supply of multi-layer circuit boards for high density mounting of semiconductors such as LSI chips and for high speed data processing circuits is strongly desired. In such multi-layer circuit board, it is important to have high reliability in electrically connecting a plurality of layers of fine pitch wiring patterns to each other and to have superior high frequency characteristics. Therefore, circuit boards having new structures and new manufacturing methods are being developed because the old ones can hardly meet such requests. In the old multi-layer circuit boards, wiring layers are electrically connected with each other by conductors plated on the inner wall of a through-hole formed by drilling, and are manufactured by the etching of copper clad laminates and the metal plating.
A method proposed by the Japanese Laid Open Patent Application No. H06-268345 is a resinous multi-layer circuit board in which all composing layers have inner-via-hole (hereinafter referred to as IVH) structure for connecting wiring layers each other. The electrical conductors of the IVH structure are formed in the manner that electrically conductive material is filled into the IVHs. In this method, the reliability of electrical connection is improved, the IVHs can be formed just under the lands for mounting electronic components, and can be formed at any portion between the wiring layers. Accordingly, size reduction of the circuit board and high density mounting can be realized.
In general, the substrate for the above circuit board is formed in the manner that aramid non-woven fabric or the like is impregnated with epoxy resin that works as insulation material. The resinous multi-layer circuit board using the above aramid non-woven fabric has the advantages of low expansion, low dielectric constant and light weight, therefore the substrate is widely used for electronic equipment for reducing the size and weight.
However, in general, in the above resinous multi-layer circuit board having IVH structure on all of the composing layers, the wiring density such as wiring pitch and wiring width are determined to have similar wiring patterns on all of the circuit boards, because the wiring patterns are formed by conventional photolithography on a resinous substrate whose top side and bottom side are plated with metal such as copper or the like.
Therefore, in the above conventional method shown in FIG. 14, the wiring density of the area for mounting chip resistors, chip capacitors or resin-packaged LSI chips 3 is determined by the shape or size of discrete components such as a chip resister, a chip capacitor and the like.
For reducing further the size of a circuit board 4, it is advisable to mount the LSI chips 3 in the form of bare chips in which the wiring density is high enough. However, if the high density area for the LSI bare chips and the relatively low density area for the discrete components are formed on one circuit board, the production yield of the circuit board becomes extremely low, which causes high cost of the circuit board.
For addressing this problem, several methods are proposed. Hereinafter the proposed methods and still existing problems are described.
The method of the Japanese Laid Open Patent Application No. H05-48231 is that a high density circuit board is set in a cavity formed on a circuit board having low wiring density. In this method, the two boards are electrically connected with each other by aligning electrical conductors of respective circuit boards, which are produced by a conventional through-hole process circuit boards. However, since all of the composing layers do not have an IVH structure, the circuit boards are electrically connected with each other through the electrical conductors exposed at the ends of the respective wiring boards. Accordingly the obtainable wiring density is not high enough in this method.
The method of the Japanese Laid Open Patent Application No. H09-46015 is that two circuit boards having respectively different wiring density are laminated. In this method, there are problems from delaying the electrical signal due to the increase of the length of the wiring lines, the increase of total thickness of the wiring boards, and that the flatness is insufficient or the height is not low enough.
The method of Japanese Laid Open Patent Application No. H09-199824 is that an opening or a cavity is formed on a multi-layer circuit board in which all of the composing layers have IVH structure. This method intended to realize high density mounting of electronic components and to decrease the height by mounting the components in the opening or in the cavity. However, in this method, the mounted components are resistors, capacitors and the like, and, it is not intended to set a circuit board having an IVH structure in the opening or in the cavity. Therefore, this method cannot realize the improvement of wiring density and production efficiency.
The method of Japanese Laid Open Patent Application No. H010-4153 is that a staircase-shape cavity is formed on a circuit board, LSI chips are set in the cavity, and the LSI chips are connected to wiring layers of the circuit board by a wire-bonding method. In this method, there are problems from delaying the electrical signal due to the increase of the length of the wiring lines, the increase of size due to unused space of the cavity, and the problems of no improvement on mounting density and production efficiency as in the above method of No. H09-199824.